7–6
Chapter 7: Using the Interfaces Library
Avalon-MM Interface Blocks
Figure 7–3 shows an example system with Avalon-MM Write FIFO and Avalon-MM
Read FIFO blocks.
Figure 7–3. Example System with Avalon-MM Write FIFO and Avalon-MM Read FIFO Blocks
Avalon-MM Write FIFO
An Avalon-MM Write FIFO has the following ports:
TestData (input). Connect this port to a Simulink block that provides simulation
data to the Avalon-MM Write FIFO. The data passes to the DataOut port one cycle
after the Ready input port asserts.
Stall (input). Connect this port to a Simulink block. It simulates stall conditions of
the Avalon-MM bus and hence underflow to the Qsys component. For any
simulation cycle where Stall asserts, the Avalon-MM Write Test Converter caches
the test data and releases in order, one sample per clock, when stall is de-asserted.
Ready (input). Connect this port to a DSP Builder block. It indicates that the
downstream hardware is ready for data.
DataOut (output). Connect this port to a DSP Builder block that corresponds to the
oldest unsent data sample received on the TestData port.
DataValid (output). Connect this port to a DSP Builder block and assert whenever
DataOut corresponds to real data.
Double-click on an Avalon-MM Write FIFO block to open the Block Parameters dialog
box so that you can set parameters for the data type, data width and FIFO depth.
1
DSP Builder Handbook
To open the hierarchy below the Avalon-MM Write FIFO block, right-click the block
and click Look Under Mask on the pop-up menu.
You can use this design as a template to design new functionality (for example, when
you use an Avalon-MM address input to split incoming streams).
November 2013 Altera Corporation
Volume 2: DSP Builder Standard Blockset
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